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Duration : 15 Days / 1 Month
Elligibility : B.E / M.E / Diploma Takeaway : Spartan3E – FPGA Development Board Free Take Away For All Trainees |
Training Contents
VLSI Foundational Concepts
Introduction to IC Technology – MOS, PMOS, NMOS, CMOS & BiCMOS technologies- Pass transistor, NMOS Inverter, Various pull ups, CMOS Inverter analysis and design-Gate realization using CMOS-Introduction to Chip Design Process- Evolution of Computer Aided Digital Design – Hardware Description Languages- Introduction to Reconfigurable Hardware -FPGA and CPLD basics- Applications of VLSI
VHDL Programming
VHDL basics – VHDL levels of abstraction – Structural , Behavioral and dataflow modes of implementation- The VHDL design flow – VHDL design entities – Entity declarations – Architectures –Concurrent signal assignments – Signal assignments with delays – Signal and variable assignments -Sequential statements – VHDL processes – Processes sensitivity lists Conditional statements – loops – selective signal assignments
Subprograms – Functions – Procedures – Differences between functions and procedures – Subprogram declarations – Packages – Package declaration – Package body. Component declarations – Component instantiation – Named port mapping – Positional port mapping –- Modeling hardware in VHDL – VHDL models for multiplexers, Encoders, Decoders, Parity Generators – combinational circuit implementation – Test bench development and VHDL Synthesis.
VERILOG Programming
System Implementation using VHDL
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VERILOG HDL Design Flow-Module Description -Lexical Conventions – Description of Data types – Net – Register- Scalar Data Description – Vector Data Description -Parameters description – Array Description – Gate level Modeling -Dataflow modeling – Behavioral Modeling -Switch level Modeling.
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System Implementation using VERILOG
Structured Procedural Statements-Always Statements-Initial Statements. Conditional statements Loops – Block Statements – Parallel block – Sequential block. VERILOG HDL implementation for combinational and Sequential digital circuits – Test Bench Implementation – Synthesis using VERILOG.